Semiconductor integrated circuits are formed by building multiple stacked layers of materials and components on a semiconductor substrate. The semiconductor devices typically include a number of electrically active components formed on the substrate. Metal conductor interconnects are formed to electrically couple the active components together by means of circuit paths or traces formed within one or more dielectric layers. Semiconductor fabrication entails a repetitive sequence of process steps including material deposition, photolithographic patterning, and material removal such as etching and ashing which gradually build the semiconductor devices. Chemical-mechanical polishing or planarization (CMP) is a technique used in semiconductor fabrication for planarization of the layer formed on the substrate in order to provide a uniform surface profile. CMP basically entails use of a polishing apparatus that is supplied with slurry which contains an abrasive, deionized water and chemical solvents, and the slurry affects the results of CMP.